diff --git a/networking/openvswitch/centos/meta_patches/0008-iommu-width-fix.patch b/networking/openvswitch/centos/meta_patches/0008-iommu-width-fix.patch
new file mode 100644
index 000000000..b0656546b
--- /dev/null
+++ b/networking/openvswitch/centos/meta_patches/0008-iommu-width-fix.patch
@@ -0,0 +1,25 @@
+From 78489fa5c3e98ac9db6244a6707622b4603bf0cb Mon Sep 17 00:00:00 2001
+From: Hayde Martinez <hayde.martinez.landa@intel.com>
+Date: Thu, 11 Oct 2018 14:44:00 -0500
+Subject: [PATCH] iommu-width-fix
+
+Signed-off-by: Hayde Martinez <hayde.martinez.landa@intel.com>
+---
+ SPECS/openvswitch.spec | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/SPECS/openvswitch.spec b/SPECS/openvswitch.spec
+index 29255d5..a3a1c87 100644
+--- a/SPECS/openvswitch.spec
++++ b/SPECS/openvswitch.spec
+@@ -108,6 +108,7 @@ ExclusiveArch: x86_64 aarch64 ppc64le s390x
+ # ovs-patches
+ Patch01: run-services-as-root-user.patch
+ Patch02: log-rotation-config.patch
++Patch03: iommu-width-fix.patch
+ 
+ # OVS (including OVN) backports (0 - 300)
+ 
+-- 
+2.7.4
+
diff --git a/networking/openvswitch/centos/meta_patches/PATCH_ORDER b/networking/openvswitch/centos/meta_patches/PATCH_ORDER
index 1c6551c98..f991a13e2 100644
--- a/networking/openvswitch/centos/meta_patches/PATCH_ORDER
+++ b/networking/openvswitch/centos/meta_patches/PATCH_ORDER
@@ -5,3 +5,4 @@
 0005-log-rotation-config.patch
 0006-rpm-check-with-condition.patch
 0007-enable-mlx-pmds.patch
+0008-iommu-width-fix.patch
diff --git a/networking/openvswitch/centos/patches/iommu-width-fix.patch b/networking/openvswitch/centos/patches/iommu-width-fix.patch
new file mode 100644
index 000000000..8a817cfe9
--- /dev/null
+++ b/networking/openvswitch/centos/patches/iommu-width-fix.patch
@@ -0,0 +1,131 @@
+--- openvswitch-2.9.0/dpdk-17.11/drivers/bus/pci/linux/pci.c	2017-11-15 18:00:28.000000000 +0000
++++ openvswitch-2.9.0p/dpdk-17.11/drivers/bus/pci/linux/pci.c	2018-10-10 17:59:58.370080207 +0000
+@@ -576,6 +576,86 @@
+ 	return 0;
+ }
+ 
++
++#if defined(RTE_ARCH_X86)
++static bool
++pci_one_device_iommu_support_va(struct rte_pci_device *dev)
++{
++#define VTD_CAP_MGAW_SHIFT	16
++#define VTD_CAP_MGAW_MASK	(0x3fULL << VTD_CAP_MGAW_SHIFT)
++#define X86_VA_WIDTH 47 /* From Documentation/x86/x86_64/mm.txt */
++	struct rte_pci_addr *addr = &dev->addr;
++	char filename[PATH_MAX];
++	FILE *fp;
++	uint64_t mgaw, vtd_cap_reg = 0;
++
++	snprintf(filename, sizeof(filename),
++		 "%s/" PCI_PRI_FMT "/iommu/intel-iommu/cap",
++		 rte_pci_get_sysfs_path(), addr->domain, addr->bus, addr->devid,
++		 addr->function);
++	if (access(filename, F_OK) == -1) {
++		/* We don't have an Intel IOMMU, assume VA supported*/
++		return true;
++	}
++
++	/* We have an intel IOMMU */
++	fp = fopen(filename, "r");
++	if (fp == NULL) {
++		RTE_LOG(ERR, EAL, "%s(): can't open %s\n", __func__, filename);
++		return false;
++	}
++
++	if (fscanf(fp, "%" PRIx64, &vtd_cap_reg) != 1) {
++		RTE_LOG(ERR, EAL, "%s(): can't read %s\n", __func__, filename);
++		fclose(fp);
++		return false;
++	}
++
++	fclose(fp);
++
++	mgaw = ((vtd_cap_reg & VTD_CAP_MGAW_MASK) >> VTD_CAP_MGAW_SHIFT) + 1;
++	if (mgaw < X86_VA_WIDTH)
++		return false;
++
++	return true;
++}
++#elif defined(RTE_ARCH_PPC_64)
++static bool
++pci_one_device_iommu_support_va(__rte_unused struct rte_pci_device *dev)
++{
++	return false;
++}
++#else
++static bool
++pci_one_device_iommu_support_va(__rte_unused struct rte_pci_device *dev)
++{
++	return true;
++}
++#endif
++
++/*
++ *  * All devices IOMMUs support VA as IOVA
++ *   */
++static bool
++pci_devices_iommu_support_va(void)
++{
++	struct rte_pci_device *dev = NULL;
++	struct rte_pci_driver *drv = NULL;
++
++	FOREACH_DRIVER_ON_PCIBUS(drv) {
++		FOREACH_DEVICE_ON_PCIBUS(dev) {
++			if (!rte_pci_match(drv, dev))
++				continue;
++			if (!pci_one_device_iommu_support_va(dev))
++				return false;
++		}
++	}
++	return true;
++}
++
++
++
++
+ /*
+  * Get iommu class of PCI devices on the bus.
+  */
+@@ -586,12 +666,7 @@
+ 	bool is_vfio_noiommu_enabled = true;
+ 	bool has_iova_va;
+ 	bool is_bound_uio;
+-	bool spapr_iommu =
+-#if defined(RTE_ARCH_PPC_64)
+-		true;
+-#else
+-		false;
+-#endif
++	bool iommu_no_va;
+ 
+ 	is_bound = pci_one_device_is_bound();
+ 	if (!is_bound)
+@@ -599,13 +674,14 @@
+ 
+ 	has_iova_va = pci_one_device_has_iova_va();
+ 	is_bound_uio = pci_one_device_bound_uio();
++	iommu_no_va = !pci_devices_iommu_support_va();
+ #ifdef VFIO_PRESENT
+ 	is_vfio_noiommu_enabled = rte_vfio_noiommu_is_enabled() == true ?
+ 					true : false;
+ #endif
+ 
+ 	if (has_iova_va && !is_bound_uio && !is_vfio_noiommu_enabled &&
+-			!spapr_iommu)
++			!iommu_no_va)
+ 		return RTE_IOVA_VA;
+ 
+ 	if (has_iova_va) {
+@@ -614,8 +690,8 @@
+ 			RTE_LOG(WARNING, EAL, "vfio-noiommu mode configured\n");
+ 		if (is_bound_uio)
+ 			RTE_LOG(WARNING, EAL, "few device bound to UIO\n");
+-		if (spapr_iommu)
+-			RTE_LOG(WARNING, EAL, "sPAPR IOMMU does not support IOVA as VA\n");
++		if (iommu_no_va)
++			RTE_LOG(WARNING, EAL, "IOMMU does not support IOVA as VA\n");
+ 	}
+ 
+ 	return RTE_IOVA_PA;
+